The present invention relates to a semiconductor memory cell using metal-oxide-silicon ("MOS") transistors, and more particularly to a structure of a dynamic random access memory ("DRAM") cell that is suitable for large scale integration and has a nondestructive read mode.
Two general types of DRAM cells include a three transistor cell shown in FIG. 1 and a one transistor cell shown in FIG. 2.
The three transistor cell 10 includes a write select line 12 (also referred to as a write row line), a read select line 14 (also referred to as a read row line), a write digit line 16 (also referred to as a write column line), a ground line 18, and a read digit line 20 (also referred to as a read column line). A write transistor 22 has a gate coupled to the write select line 12 and a controlled node coupled to write digit line 16. (The drain and source of MOS transistors are referred to as "controlled nodes" since MOS transistors are symmetrical. The drain and source have no independent significance and are determined solely by the applied voltages.) An amplifying transistor 24 has a gate coupled to the other controlled node of the write transistor 22 to define a charge storage node 28. The parasitic capacitance of node 28 is used to store the charge. Additional capacitance can be used if desired, but this increases cell size. One controlled node of amplifying transistor 24 is coupled to ground line 18. A read transistor 26 has a controlled node coupled to the other controlled node of amplifying transistor 24, a gate coupled to the read select line 14, and another controlled node coupled to the read digit line 20.
The characteristic feature of the three transistor cell 10 is that data stored on the charge storage node 28 is nondestructively read out to the read digit line 20. Note that there is no resistive path from charge storage node 28 to the read digit line 20. However, the nondestructive readout and the benefit of the amplifying transistor 24 are at the price of memory cell size. Note that three transistors and five lines are required for each memory cell 10. Therefore, the three transistor memory cell has limited applications in large scale integration.
In place of the three transistor memory cell 10 described above, a one transistor, one capacitor memory cell 30 is shown in FIG. 2. A single transistor 38 has combined read and write functions. The gate of transistor 38 is coupled to a select line 32 (also referred to as a row line) and one controlled node of transistor 38 is coupled to a digit line 34 (also referred to as a column line). The other controlled node of transistor 38 is coupled to one plate of an integrated capacitor 40. The other plate of the capacitor is coupled to VDD, typically five volts, or some other reference voltage between five volts and ground. The data that is written into and read out of memory cell 30 is stored on integrated capacitor 40. Note that capacitor 40 is not the parasitic capacitance of transistor 38, but a separate circuit element.
Thus, memory cell 30 includes three lines, one transistor and one capacitor. The size of the one transistor memory cell 30 is highly desirable for large scale integration. However, data stored on capacitor 40 is destructively read out of memory cell 30 since there is a resistive path through transistor 38 from the capacitor 40 to the digit line 34.
What is desired is a memory cell having a nondestructive readout feature, yet having a minimum cell area suitable for large scale integration on an integrated memory array.